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Author SHA1 Message Date
feng-arch
ce5f11102e modify README.md 2025-09-18 11:58:12 +08:00
feng-arch
86ab374569 feat: 做了一些调整,加了两个示例,这两个示例都跑不过,仿真器内部的迭代方法是错的 2025-09-18 11:56:14 +08:00
feng-arch
10bca9eafc add a new method for NR loop, only diode have finished, 2024-08-22 11:37:28 +08:00
feng-arch
633fd2aa7e 添加了vcr器件,该器件由电阻改造而来,但是没有解决电阻为0的情况(之后的思路:加一个电压源的branch,在该branch上,当电阻为0时,给电导一个比较大的值,然后给其并联一个电压源) 2024-08-18 23:26:08 +08:00
feng-arch
bd01f3ffe0 修改了VCCS中存在的bug,vccs在load_static_G中output和control port反了,已修正,田间test_16b函数,对应施老师课程中的Lecture6_B作业部分 2024-08-18 20:25:04 +08:00
feng-arch
e4bca0be72 第一次提交,完整的sim,支持R,L,C,Dio,Mos等简单器件 2024-08-18 16:17:00 +08:00
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