fengqi/lv_micropython
1
0
Fork 0
Code Issues Pull Requests 1 Actions Packages Projects Releases Wiki Activity

tools/mpy_ld.py: Ignore R_XTENSA_ASM_EXPAND relocation entries.

Browse Source 
As reported in #14430 the Xtensa compiler can add R_XTENSA_ASM_EXPAND
relocation relaxation entries in object files, and they were not
supported by mpy_ld.

This commit adds handling for that entry, doing nothing with it, as it
is only of real use for an optimising linker.

Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit is contained in:
Alessandro Gatti 2024-08-28 15:05:47 +02:00 committed by Damien George
parent e370999e37
commit a831c788f7
1 changed files with 8 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
tools/mpy_ld.py
View File

@ -69,6 +69,7 @@ R_XTENSA_PLT = 6
R_386_GOTOFF = 9 R_386_GOTOFF = 9
R_386_GOTPC = 10 R_386_GOTPC = 10
R_ARM_THM_CALL = 10 R_ARM_THM_CALL = 10
R_XTENSA_ASM_EXPAND = 11
R_XTENSA_DIFF32 = 19 R_XTENSA_DIFF32 = 19
R_XTENSA_SLOT0_OP = 20 R_XTENSA_SLOT0_OP = 20
R_ARM_BASE_PREL = 25 # aka R_ARM_GOTPC R_ARM_BASE_PREL = 25 # aka R_ARM_GOTPC
@ -562,9 +563,14 @@ def do_relocation_text(env, text_addr, r):
reloc = addr - r_offset reloc = addr - r_offset
reloc_type = "xtensa_l32r" reloc_type = "xtensa_l32r"
elif env.arch.name == "EM_XTENSA" and r_info_type in (R_XTENSA_DIFF32, R_XTENSA_PDIFF32): elif env.arch.name == "EM_XTENSA" and r_info_type in (
R_XTENSA_DIFF32,
R_XTENSA_PDIFF32,
R_XTENSA_ASM_EXPAND,
):
if s.section.name.startswith(".text"): if s.section.name.startswith(".text"):
# it looks like R_XTENSA_[P]DIFF32 into .text is already correctly relocated # it looks like R_XTENSA_[P]DIFF32 into .text is already correctly relocated,
# and expand relaxations cannot occur in non-executable sections.
return return
assert 0 assert 0