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lv_micropython/ports/stm32/boards/stm32f091_af.csv
Jim Mussared 286b1b3ed9 stm32/boards: Format stm32 alternate function csv files. 
Changes are:
- Pad all cells to make them easier to read.
- Ensure all files have exactly 19 columns (Port,Pin,AF0-15,ADC)

This work was funded through GitHub Sponsors.

Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
2023-11-03 14:08:39 +11:00

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1Port Pin AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 ADC
2AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 ADC
3PortAPA0 USART2_CTS TIM2_CH1_ETR TSC_G1_IO1USART4_TX COMP1_OUTADC1_IN0
4PortAPA1 EVENTOUT USART2_RTS TIM2_CH2 TSC_G1_IO2USART4_RX TIM15_CH1N ADC1_IN1
5PortAPA2 TIM15_CH1 USART2_TX TIM2_CH3 TSC_G1_IO3COMP2_OUTADC1_IN2
6PortAPA3 TIM15_CH2 USART2_RX TIM2_CH4 TSC_G1_IO4ADC1_IN3
7PortAPA4 SPI1_NSS/I2S1_WS USART2_CK TSC_G2_IO1TIM14_CH1 USART6_TX ADC1_IN4
8PortAPA5 SPI1_SCK/I2S1_CK CEC TIM2_CH1_ETR TSC_G2_IO2USART6_RX ADC1_IN5
9PortAPA6 SPI1_MISO/I2S1_MCKTIM3_CH1 TIM1_BKIN TSC_G2_IO3USART3_CTS TIM16_CH1 EVENTOUTCOMP1_OUTADC1_IN6
10PortAPA7 SPI1_MOSI/I2S1_SD TIM3_CH2 TIM1_CH1N TSC_G2_IO4TIM14_CH1 TIM17_CH1 EVENTOUTCOMP2_OUTADC1_IN7
11PortAPA8 MCO USART1_CK TIM1_CH1 EVENTOUT CRS_SYNC
12PortAPA9 TIM15_BKIN USART1_TX TIM1_CH2 TSC_G4_IO1I2C1_SCL MCO
13PortAPA10TIM17_BKIN USART1_RX TIM1_CH3 TSC_G4_IO2I2C1_SDA
14PortAPA11EVENTOUT USART1_CTS TIM1_CH4 TSC_G4_IO3CAN1_RX I2C2_SCL COMP1_OUT
15PortAPA12EVENTOUT USART1_RTS TIM1_ETR TSC_G4_IO4CAN1_TX I2C2_SDA COMP2_OUT
16PortAPA13SWDIO IR_OUT
17PortAPA14SWCLK USART2_TX
18PortAPA15SPI1_NSS/I2S1_WS USART2_RX TIM2_CH1_ETR EVENTOUT USART4_RTS
19PortBPB0 EVENTOUT TIM3_CH3 TIM1_CH2N TSC_G3_IO2USART3_CK ADC1_IN8
20PortBPB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N TSC_G3_IO3USART3_RTS ADC1_IN9
21PortBPB2 TSC_G3_IO4
22PortBPB3 SPI1_SCK/I2S1_CK EVENTOUT TIM2_CH2 TSC_G5_IO1USART5_TX
23PortBPB4 SPI1_MISO/I2S1_MCKTIM3_CH1 EVENTOUT TSC_G5_IO2USART5_RX TIM17_BKIN
24PortBPB5 SPI1_MOSI/I2S1_SD TIM3_CH2 TIM16_BKIN I2C1_SMBA USART5_CK/USART5_RTS
25PortBPB6 USART1_TX I2C1_SCL TIM16_CH1N TSC_G5_IO3
26PortBPB7 USART1_RX I2C1_SDA TIM17_CH1N TSC_G5_IO4USART4_CTS
27PortBPB8 CEC I2C1_SCL TIM16_CH1 TSC_SYNC CAN1_RX
28PortBPB9 IR_OUT I2C1_SDA TIM17_CH1 EVENTOUT CAN1_TX SPI2_NSS/I2S2_WS
29PortBPB10CEC I2C2_SCL TIM2_CH3 TSC_SYNC USART3_TX SPI2_SCK/I2S2_CK
30PortBPB11EVENTOUT I2C2_SDA TIM2_CH4 TSC_G6_IO1USART3_RX
31PortBPB12SPI2_NSS/I2S2_WS EVENTOUT TIM1_BKIN TSC_G6_IO2USART3_CK TIM15_BKIN
32PortBPB13SPI2_SCK/I2S2_CK TIM1_CH1N TSC_G6_IO3USART3_CTS I2C2_SCL
33PortBPB14SPI2_MISO/I2S2_MCKTIM15_CH1 TIM1_CH2N TSC_G6_IO4USART3_RTS I2C2_SDA
34PortBPB15SPI2_MOSI/I2S2_SD TIM15_CH2 TIM1_CH3N TIM15_CH1N
35PortCPC0 EVENTOUT USART7_TX USART6_TX ADC1_IN10
36PortCPC1 EVENTOUT USART7_RX USART6_RX ADC1_IN11
37PortCPC2 EVENTOUT SPI2_MISO/I2S2_MCK USART8_TX ADC1_IN12
38PortCPC3 EVENTOUT SPI2_MOSI/I2S2_SD USART8_RX ADC1_IN13
39PortCPC4 EVENTOUT USART3_TX ADC1_IN14
40PortCPC5 TSC_G3_IO1 USART3_RX ADC1_IN15
41PortCPC6 TIM3_CH1 USART7_TX
42PortCPC7 TIM3_CH2 USART7_RX
43PortCPC8 TIM3_CH3 USART8_TX
44PortCPC9 TIM3_CH4 USART8_RX
45PortCPC10USART4_TX USART3_TX
46PortCPC11USART4_RX USART3_RX
47PortCPC12USART4_CK USART3_CK USART5_TX
48PortCPC13
49PortCPC14
50PortCPC15
51PortDPD0 CAN1_RX SPI2_NSS/I2S2_WS
52PortDPD1 CAN1_TX SPI2_SCK/I2S2_CK
53PortDPD2 TIM3_ETR USART3_RTS USART5_RX
54PortDPD3 USART2_CTS SPI2_MISO/I2S2_MCK
55PortDPD4 USART2_RTS SPI2_MOSI/I2S2_SD
56PortDPD5 USART2_TX
57PortDPD6 USART2_RX
58PortDPD7 USART2_CK
59PortDPD8 USART3_TX
60PortDPD9 USART3_RX
61PortDPD10USART3_CK
62PortDPD11USART3_CTS
63PortDPD12USART3_RTS TSC_G8_IO1 USART8_CK/USART8_RTS
64PortDPD13USART8_TX TSC_G8_IO2
65PortDPD14USART8_RX TSC_G8_IO3
66PortDPD15CRS_SYNC TSC_G8_IO4 USART7_CK/USART7_RTS
67PortEPE0 TIM16_CH1 EVENTOUT
68PortEPE1 TIM17_CH1 EVENTOUT
69PortEPE2 TIM3_ETR TSC_G7_IO1
70PortEPE3 TIM3_CH1 TSC_G7_IO2
71PortEPE4 TIM3_CH2 TSC_G7_IO3
72PortEPE5 TIM3_CH3 TSC_G7_IO4
73PortEPE6 TIM3_CH4
74PortEPE7 TIM1_ETR USART5_CK/USART5_RTS
75PortEPE8 TIM1_CH1N USART4_TX
76PortEPE9 TIM1_CH1 USART4_RX
77PortEPE10TIM1_CH2N USART5_TX
78PortEPE11TIM1_CH2 USART5_RX
79PortEPE12TIM1_CH3N SPI1_NSS/I2S1_WS
80PortEPE13TIM1_CH3 SPI1_SCK/I2S1_CK
81PortEPE14TIM1_CH4 SPI1_MISO/I2S1_MCK
82PortEPE15TIM1_BKIN SPI1_MOSI/I2S1_SD
83PortFPF0 CRS_SYNC I2C1_SDA
84PortFPF1 I2C1_SCL
85PortFPF2 EVENTOUT USART7_TX USART7_CK/USART7_RTS
86PortFPF3 EVENTOUT USART7_RX USART6_CK/USART6_RTS
87PortFPF6
88PortFPF9 TIM15_CH1 USART6_TX
89PortFPF10TIM15_CH2 USART6_RX
90PortFPF11