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lv_micropython/ports/stm32/boards/stm32g0b1_af.csv
Jim Mussared 286b1b3ed9 stm32/boards: Format stm32 alternate function csv files. 
Changes are:
- Pad all cells to make them easier to read.
- Ensure all files have exactly 19 columns (Port,Pin,AF0-15,ADC)

This work was funded through GitHub Sponsors.

Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
2023-11-03 14:08:39 +11:00

29 KiB
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1Port Pin AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11AF12AF13AF14AF15ADC
2AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11AF12AF13AF14AF15ADC
3PortAPA0 SPI2_SCK/I2S2_CK USART2_CTS TIM2_CH1/TIM2_ETRUSART4_TX LPTIM1_OUT UCPD2_FRSTX COMP1_OUTADC1_IN0
4PortAPA1 SPI1_SCK/I2S1_CK USART2_RTS/USART2_DE/USART2_CKTIM2_CH2 USART4_RX TIM15_CH1N I2C1_SMBA EVENTOUT ADC1_IN1
5PortAPA2 SPI1_MOSI/I2S1_SD USART2_TX TIM2_CH3 UCPD1_FRSTX TIM15_CH1 LPUART1_TX COMP2_OUTADC1_IN2
6PortAPA3 SPI2_MISO/I2S2_MCK USART2_RX TIM2_CH4 UCPD2_FRSTX TIM15_CH2 LPUART1_RX EVENTOUT ADC1_IN3
7PortAPA4 SPI1_NSS/I2S1_WS SPI2_MOSI/I2S2_SD USB_NOE USART6_TX TIM14_CH1 LPTIM2_OUT UCPD2_FRSTX EVENTOUT SPI3_NSS ADC1_IN4
8PortAPA5 SPI1_SCK/I2S1_CK CEC TIM2_CH1/TIM2_ETRUSART6_RX USART3_TX LPTIM2_ETR UCPD1_FRSTX EVENTOUT ADC1_IN5
9PortAPA6 SPI1_MISO/I2S1_MCK TIM3_CH1 TIM1_BKIN USART6_CTS USART3_CTS TIM16_CH1 LPUART1_CTS COMP1_OUTI2C2_SDA I2C3_SDA ADC1_IN6
10PortAPA7 SPI1_MOSI/I2S1_SD TIM3_CH2 TIM1_CH1N USART6_RTS/USART6_DE/USART6_CKTIM14_CH1 TIM17_CH1 UCPD1_FRSTX COMP2_OUTI2C2_SCL I2C3_SCL ADC1_IN7
11PortAPA8 MCO SPI2_NSS/I2S2_WS TIM1_CH1 CRS1_SYNC LPTIM2_OUT EVENTOUT I2C2_SMBA
12PortAPA9 MCO USART1_TX TIM1_CH2 SPI2_MISO/I2S2_MCK TIM15_BKIN I2C1_SCL EVENTOUT I2C2_SCL
13PortAPA10SPI2_MOSI/I2S2_SD USART1_RX TIM1_CH3 MCO2 TIM17_BKIN I2C1_SDA EVENTOUT I2C2_SDA
14PortAPA11SPI1_MISO/I2S1_MCK USART1_CTS TIM1_CH4 FDCAN1_RX TIM1_BKIN2 I2C2_SCL COMP1_OUT
15PortAPA12SPI1_MOSI/I2S1_SD USART1_RTS/USART1_DE/USART1_CKTIM1_ETR FDCAN1_TX I2S_CKIN I2C2_SDA COMP2_OUT
16PortAPA13SWDIO IR_OUT USB_NOE EVENTOUT LPUART2_RX
17PortAPA14SWCLK USART2_TX EVENTOUT LPUART2_TX
18PortAPA15SPI1_NSS/I2S1_WS USART2_RX TIM2_CH1/TIM2_ETRMCO2 USART4_RTS/USART4_DE/USART4_CKUSART3_RTS/USART3_DE/USART3_CKUSB_NOE EVENTOUT I2C2_SMBA SPI3_NSS
19PortBPB0 SPI1_NSS/I2S1_WS TIM3_CH3 TIM1_CH2N FDCAN2_RX USART3_RX LPTIM1_OUT UCPD1_FRSTX COMP1_OUTUSART5_TX LPUART2_CTS ADC1_IN8
20PortBPB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N FDCAN2_TX USART3_RTS/USART3_DE/USART3_CKLPTIM2_IN1 LPUART1_RTS/LPUART1_DECOMP3_OUTUSART5_RX LPUART2_RTS/LPUART2_DEADC1_IN9
21PortBPB2 SPI2_MISO/I2S2_MCK MCO2 USART3_TX LPTIM1_OUT EVENTOUT ADC1_IN10
22PortBPB3 SPI1_SCK/I2S1_CK TIM1_CH2 TIM2_CH2 USART5_TX USART1_RTS/USART1_DE/USART1_CKI2C3_SCL EVENTOUT I2C2_SCL SPI3_SCK
23PortBPB4 SPI1_MISO/I2S1_MCK TIM3_CH1 USART5_RX USART1_CTS TIM17_BKIN I2C3_SDA EVENTOUT I2C2_SDA SPI3_MISO
24PortBPB5 SPI1_MOSI/I2S1_SD TIM3_CH2 TIM16_BKIN FDCAN2_RX LPTIM1_IN1 I2C1_SMBA COMP2_OUTUSART5_RTS/USART5_DE/USART5_CKSPI3_MOSI
25PortBPB6 USART1_TX TIM1_CH3 TIM16_CH1N FDCAN2_TX SPI2_MISO/I2S2_MCK LPTIM1_ETR I2C1_SCL EVENTOUT USART5_CTS TIM4_CH1 LPUART2_TX
26PortBPB7 USART1_RX SPI2_MOSI/I2S2_SD TIM17_CH1N USART4_CTS LPTIM1_IN2 I2C1_SDA EVENTOUT TIM4_CH2 LPUART2_RX
27PortBPB8 CEC SPI2_SCK/I2S2_CK TIM16_CH1 FDCAN1_RX USART3_TX TIM15_BKIN I2C1_SCL EVENTOUT USART6_TX TIM4_CH3
28PortBPB9 IR_OUT UCPD2_FRSTX TIM17_CH1 FDCAN1_TX USART3_RX SPI2_NSS/I2S2_WS I2C1_SDA EVENTOUT USART6_RX TIM4_CH4
29PortBPB10CEC LPUART1_RX TIM2_CH3 USART3_TX SPI2_SCK/I2S2_CK I2C2_SCL COMP1_OUTADC1_IN11
30PortBPB11SPI2_MOSI/I2S2_SD LPUART1_TX TIM2_CH4 USART3_RX I2C2_SDA COMP2_OUT
31PortBPB12SPI2_NSS/I2S2_WS LPUART1_RTS/LPUART1_DE TIM1_BKIN FDCAN2_RX TIM15_BKIN UCPD2_FRSTX EVENTOUT I2C2_SMBA
32PortBPB13SPI2_SCK/I2S2_CK LPUART1_CTS TIM1_CH1N FDCAN2_TX USART3_CTS TIM15_CH1N I2C2_SCL EVENTOUT
33PortBPB14SPI2_MISO/I2S2_MCK UCPD1_FRSTX TIM1_CH2N USART3_RTS/USART3_DE/USART3_CKTIM15_CH1 I2C2_SDA EVENTOUT USART6_RTS/USART6_DE/USART6_CK
34PortBPB15SPI2_MOSI/I2S2_SD TIM1_CH3N TIM15_CH1N TIM15_CH2 EVENTOUT USART6_CTS
35PortCPC0 LPTIM1_IN1 LPUART1_RX LPTIM2_IN1 LPUART2_TX USART6_TX I2C3_SCL COMP3_OUT
36PortCPC1 LPTIM1_OUT LPUART1_TX TIM15_CH1 LPUART2_RX USART6_RX I2C3_SDA
37PortCPC2 LPTIM1_IN2 SPI2_MISO/I2S2_MCK TIM15_CH2 FDCAN2_RX COMP3_OUT
38PortCPC3 LPTIM1_ETR SPI2_MOSI/I2S2_SD LPTIM2_ETR FDCAN2_TX
39PortCPC4 USART3_TX USART1_TX TIM2_CH1/TIM2_ETRFDCAN1_RX
40PortCPC5 USART3_RX USART1_RX TIM2_CH2 FDCAN1_TX ADC1_IN18
41PortCPC6 UCPD1_FRSTX TIM3_CH1 TIM2_CH3 LPUART2_TX
42PortCPC7 UCPD2_FRSTX TIM3_CH2 TIM2_CH4 LPUART2_RX
43PortCPC8 UCPD2_FRSTX TIM3_CH3 TIM1_CH1 LPUART2_CTS
44PortCPC9 I2S_CKIN TIM3_CH4 TIM1_CH2 LPUART2_RTS/LPUART2_DE USB_NOE
45PortCPC10USART3_TX USART4_TX TIM1_CH3 SPI3_SCK
46PortCPC11USART3_RX USART4_RX TIM1_CH4 SPI3_MISO
47PortCPC12LPTIM1_IN1 UCPD1_FRSTX TIM14_CH1 USART5_TX SPI3_MOSI
48PortCPC13TIM1_BKIN
49PortCPC14TIM1_BKIN2
50PortCPC15OSC32_EN OSC_EN TIM15_BKIN
51PortDPD0 EVENTOUT SPI2_NSS/I2S2_WS TIM16_CH1 FDCAN1_RX
52PortDPD1 EVENTOUT SPI2_SCK/I2S2_CK TIM17_CH1 FDCAN1_TX
53PortDPD2 USART3_RTS/USART3_DE/USART3_CKTIM3_ETR TIM1_CH1N USART5_RX
54PortDPD3 USART2_CTS SPI2_MISO/I2S2_MCK TIM1_CH2N USART5_TX
55PortDPD4 USART2_RTS/USART2_DE/USART2_CKSPI2_MOSI/I2S2_SD TIM1_CH3N USART5_RTS/USART5_DE/USART5_CK
56PortDPD5 USART2_TX SPI1_MISO/I2S1_MCK TIM1_BKIN USART5_CTS
57PortDPD6 USART2_RX SPI1_MOSI/I2S1_SD LPTIM2_OUT
58PortDPD7 MCO2
59PortDPD8 USART3_TX SPI1_SCK/I2S1_CK LPTIM1_OUT
60PortDPD9 USART3_RX SPI1_NSS/I2S1_WS TIM1_BKIN2
61PortDPD10MCO
62PortDPD11USART3_CTS LPTIM2_ETR
63PortDPD12USART3_RTS/USART3_DE/USART3_CKLPTIM2_IN1 TIM4_CH1 FDCAN1_RX
64PortDPD13LPTIM2_OUT TIM4_CH2 FDCAN1_TX
65PortDPD14LPUART2_CTS TIM4_CH3 FDCAN2_RX
66PortDPD15CRS1_SYNC LPUART2_RTS/LPUART2_DE TIM4_CH4 FDCAN2_TX
67PortEPE0 TIM16_CH1 EVENTOUT TIM4_ETR
68PortEPE1 TIM17_CH1 EVENTOUT
69PortEPE2 TIM3_ETR
70PortEPE3 TIM3_CH1
71PortEPE4 TIM3_CH2
72PortEPE5 TIM3_CH3
73PortEPE6 TIM3_CH4
74PortEPE7 TIM1_ETR USART5_RTS/USART5_DE/USART5_CK
75PortEPE8 USART4_TX TIM1_CH1N
76PortEPE9 USART4_RX TIM1_CH1
77PortEPE10TIM1_CH2N USART5_TX
78PortEPE11TIM1_CH2 USART5_RX
79PortEPE12SPI1_NSS/I2S1_WS TIM1_CH3N
80PortEPE13SPI1_SCK/I2S1_CK TIM1_CH3
81PortEPE14SPI1_MISO/I2S1_MCK TIM1_CH4 TIM1_BK2
82PortEPE15SPI1_MOSI/I2S1_SD TIM1_BK
83PortFPF0 CRS1_SYNC EVENTOUT TIM14_CH1
84PortFPF1 OSC_EN EVENTOUT TIM15_CH1N
85PortFPF2 MCO LPUART2_TX LPUART2_RTS/LPUART2_DE
86PortFPF3 LPUART2_RX USART6_RTS/USART6_DE/USART6_CK
87PortFPF4 LPUART1_TX
88PortFPF5 LPUART1_RX
89PortFPF6 LPUART1_RTS/LPUART1_DE
90PortFPF7 LPUART1_CTS USART5_CTS
91PortFPF8
92PortFPF9 USART6_TX
93PortFPF10USART6_RX
94PortFPF11USART6_RTS/USART6_DE/USART6_CK
95PortFPF12TIM15_CH1 USART6_CTS
96PortFPF13TIM15_CH2