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lv_micropython/ports/stm32/boards/stm32l152_af.csv
Jim Mussared 286b1b3ed9 stm32/boards: Format stm32 alternate function csv files. 
Changes are:
- Pad all cells to make them easier to read.
- Ensure all files have exactly 19 columns (Port,Pin,AF0-15,ADC)

This work was funded through GitHub Sponsors.

Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
2023-11-03 14:08:39 +11:00

21 KiB
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1Port Pin AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9AF10AF11AF12AF13AF14AF15 ADC
2SYS_AF TIM2 TIM3/TIM4/TIM5TIM9/TIM10/TIM11I2C1/I2C2SPI1/SPI2 SPI3 USART1/USART2/USART3UART4/UART5ADC
3PortAPA0 TIM2_CH1_ETRTIM5_CH1 USART2_CTS EVENTOUTADC1_IN0
4PortAPA1 TIM2_CH2 TIM5_CH2 USART2_RTS EVENTOUTADC1_IN1
5PortAPA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX EVENTOUTADC1_IN2
6PortAPA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_RX EVENTOUTADC1_IN3
7PortAPA4 SPI1_NSS SPI3_NSS/I2S3_WS USART2_CK EVENTOUTADC1_IN4
8PortAPA5 TIM2_CH1_ETRSPI1_SCK EVENTOUTADC1_IN5
9PortAPA6 TIM3_CH1 TIM10_CH1 SPI1_MISO EVENTOUTADC1_IN6
10PortAPA7 TIM3_CH2 TIM11_CH1 SPI1_MOSI EVENTOUTADC1_IN7
11PortAPA8 MCO USART1_CK EVENTOUT
12PortAPA9 USART1_TX EVENTOUT
13PortAPA10USART1_RX EVENTOUT
14PortAPA11SPI1_MISO USART1_CTS EVENTOUT
15PortAPA12SPI1_MOSI USART1_RTS EVENTOUT
16PortAPA13JTMS/SWDIOEVENTOUT
17PortAPA14JTCK/SWCLKEVENTOUT
18PortAPA15JTDI TIM2_CH1_ETRSPI1_NSS SPI3_NSS/I2S3_WS EVENTOUT
19PortBPB0 TIM3_CH3 EVENTOUTADC1_IN8
20PortBPB1 TIM3_CH4 EVENTOUTADC1_IN9
21PortBPB2 BOOT1 EVENTOUT
22PortBPB3 JTDO TIM2_CH2 SPI1_SCK SPI3_SCK/I2S3_CK EVENTOUT
23PortBPB4 NJTRST TIM3_CH1 SPI1_MISO SPI3_MISO EVENTOUT
24PortBPB5 TIM3_CH2 I2C1_SMBASPI1_MOSI SPI3_MOSI/I2S3_SDEVENTOUT
25PortBPB6 TIM4_CH1 I2C1_SCL USART1_TX EVENTOUT
26PortBPB7 TIM4_CH2 I2C1_SDA USART1_RX EVENTOUT
27PortBPB8 TIM4_CH3 TIM10_CH1 I2C1_SCL EVENTOUT
28PortBPB9 TIM4_CH4 TIM11_CH1 I2C1_SDA EVENTOUT
29PortBPB10TIM2_CH3 I2C2_SCL USART3_TX EVENTOUT
30PortBPB11TIM2_CH4 I2C2_SDA USART3_RX EVENTOUT
31PortBPB12TIM10_CH1 I2C2_SMBASPI2_NSS/I2S2_WS USART3_CK EVENTOUTADC1_IN18
32PortBPB13TIM9_CH1 SPI2_SCK/I2S2_CK USART3_CTS EVENTOUTADC1_IN19
33PortBPB14TIM9_CH2 SPI2_MISO USART3_RTS EVENTOUTADC1_IN20
34PortBPB15TIM11_CH1 SPI2_MOSI/I2S2_SDEVENTOUTADC1_IN21
35PortCPC0 EVENTOUTADC1_IN10
36PortCPC1 EVENTOUTADC1_IN11
37PortCPC2 EVENTOUTADC1_IN12
38PortCPC3 EVENTOUTADC1_IN13
39PortCPC4 EVENTOUTADC1_IN14
40PortCPC5 EVENTOUTADC1_IN15
41PortCPC6 TIM3_CH1 I2S2_MCK EVENTOUT
42PortCPC7 TIM3_CH2 I2S3_MCK EVENTOUT
43PortCPC8 TIM3_CH3 EVENTOUT
44PortCPC9 TIM3_CH4 EVENTOUT
45PortCPC10SPI3_SCK/I2S3_CK USART3_TX UART4_TX EVENTOUT
46PortCPC11SPI3_MISO USART3_RX UART4_RX EVENTOUT
47PortCPC12SPI3_MOSI/I2S3_SDUSART3_CK UART5_TX EVENTOUT
48PortCPC13EVENTOUT
49PortCPC14EVENTOUT
50PortCPC15EVENTOUT
51PortDPD0 TIM9_CH1 SPI2_NSS/I2S2_WS EVENTOUT
52PortDPD1 SPI2_SCK/I2S2_CK EVENTOUT
53PortDPD2 TIM3_ETR UART5_RX EVENTOUT
54PortDPD3 SPI2_MISO USART2_CTS EVENTOUT
55PortDPD4 SPI2_MOSI/I2S2_SDUSART2_RTS EVENTOUT
56PortDPD5 USART2_TX EVENTOUT
57PortDPD6 USART2_RX EVENTOUT
58PortDPD7 TIM9_CH2 USART2_CK EVENTOUT
59PortDPD8 USART3_TX EVENTOUT
60PortDPD9 USART3_RX EVENTOUT
61PortDPD10USART3_CK EVENTOUT
62PortDPD11USART3_CTS EVENTOUT
63PortDPD12TIM4_CH1 USART3_RTS EVENTOUT
64PortDPD13TIM4_CH2 EVENTOUT
65PortDPD14TIM4_CH3 EVENTOUT
66PortDPD15TIM4_CH4 EVENTOUT
67PortEPE0 TIM4_ETR TIM10_CH1 EVENTOUT
68PortEPE1 TIM11_CH1 EVENTOUT
69PortEPE2 TRACECK TIM3_ETR EVENTOUT
70PortEPE3 TRACED0 TIM3_CH1 EVENTOUT
71PortEPE4 TRACED1 TIM3_CH2 EVENTOUT
72PortEPE5 TRACED2 TIM9_CH1 EVENTOUT
73PortEPE6 TRACED3 TIM9_CH2 EVENTOUT
74PortEPE7 EVENTOUT
75PortEPE8 EVENTOUT
76PortEPE9 TIM2_CH1_ETREVENTOUT
77PortEPE10TIM2_CH2 EVENTOUT
78PortEPE11TIM2_CH3 EVENTOUT
79PortEPE12TIM2_CH4 SPI1_NSS EVENTOUT
80PortEPE13SPI1_SCK EVENTOUT
81PortEPE14SPI1_MISO EVENTOUT
82PortEPE15SPI1_MOSI EVENTOUT
83PortFPF0 EVENTOUT
84PortFPF1 EVENTOUT
85PortFPF2 EVENTOUT
86PortFPF3 EVENTOUT
87PortFPF4 EVENTOUT
88PortFPF5 EVENTOUT
89PortFPF6 TIM5_ETR EVENTOUT
90PortFPF7 TIM5_CH2 EVENTOUT
91PortFPF8 TIM5_CH3 EVENTOUT
92PortFPF9 TIM5_CH4 EVENTOUT
93PortFPF10EVENTOUT
94PortFPF11EVENTOUT
95PortFPF12EVENTOUT
96PortFPF13EVENTOUT
97PortFPF14EVENTOUT
98PortFPF15EVENTOUT
99PortGPG0 EVENTOUT
100PortGPG1 EVENTOUT
101PortGPG2 EVENTOUT
102PortGPG3 EVENTOUT
103PortGPG4 EVENTOUT
104PortGPG5 EVENTOUT
105PortGPG6 EVENTOUT
106PortGPG7 EVENTOUT
107PortGPG8 EVENTOUT
108PortGPG9 EVENTOUT
109PortGPG10EVENTOUT
110PortGPG11EVENTOUT
111PortGPG12EVENTOUT
112PortGPG13EVENTOUT
113PortGPG14EVENTOUT
114PortGPG15EVENTOUT
115PortHPH0
116PortHPH1
117PortHPH2