659113825d
Because this port now supports multiple architectures. Signed-off-by: Damien George <damien@micropython.org>
45 lines
769 B
Plaintext
45 lines
769 B
Plaintext
/* This file is part of the MicroPython project, http://micropython.org/
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* The MIT License (MIT)
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* Copyright (c) 2018 Damien P. George
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*/
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MEMORY
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{
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ROM : ORIGIN = 0x00000000, LENGTH = 1M
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RAM : ORIGIN = 0x20000000, LENGTH = 128K
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}
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_estack = ORIGIN(RAM) + LENGTH(RAM);
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SECTIONS
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{
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.text : {
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. = ALIGN(4);
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KEEP(*(.isr_vector))
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*(.text*)
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*(.rodata*)
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. = ALIGN(4);
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_etext = .;
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_sidata = _etext;
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} > ROM
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.data : AT ( _sidata )
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{
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. = ALIGN(4);
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_sdata = .;
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*(.data*)
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. = ALIGN(4);
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_edata = .;
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} >RAM
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.bss :
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{
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. = ALIGN(4);
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_sbss = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = .;
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} >RAM
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}
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