Alessandro Gatti 3dd1130f6d py/emitnative: Emit better load/store sequences for RISC-V RV32IMC.
Selected load/store code sequences have been optimised for RV32IMC when the
chance to use fewer and smaller opcodes was possible.

Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
2024-06-21 15:06:52 +10:00
..
2024-06-06 17:34:28 +10:00
2024-06-06 17:34:28 +10:00
2023-06-02 21:50:57 +10:00
2024-06-06 17:34:28 +10:00